SH7261 Datasheet, PDF (857/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Bit 10 - 8 — Test Mode (TST[2:0]): This bit enables/disables the test modes. Please note that
before activating the Test Mode it is requested to move RCAN-ET into Halt mode or Reset mode.
This is to avoid that the transition to Test Mode could affect a transmission/reception in progress.
For details, please refer to section 19.6.2, Test Mode Settings.
Please note that the test modes are allowed only for diagnosis and tests and not when RCAN-ET is
used in normal operation.
Bit10:
TST2
0
0
0
0
1
1
1
1
Bit9:
TST1
0
0
1
1
0
0
1
1
Bit8:
TST0
0
1
0
1
0
1
0
1
Description
Normal mode (initial value)
Listen-only mode (receive-only mode)
Self test mode 1 (external)
Self test mode 2 (internal)
Write error counter
Error passive mode
Setting prohibited
Setting prohibited
Bit 7 — Auto-wake Mode (MCR7): MCR7 enables or disables the Auto-wake mode. If this bit is
set, the RCAN-ET automatically cancels the sleep mode (MCR5) by detecting CAN bus activity
(dominant bit). If MCR7 is cleared the RCAN-ET does not automatically cancel the sleep mode.
RCAN-ET cannot store the message that wakes it up.
Note: MCR7 cannot be modified while in sleep mode.
Bit7: MCR7
0
1
Description
Auto-wake by CAN bus activity disabled (Initial value)
Auto-wake by CAN bus activity enabled
Rev. 2.00 Sep. 07, 2007 Page 825 of 1312
REJ09B0320-0200