SH7261 Datasheet, PDF (41/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Item
Features
CD-ROM decoder
(ROM-DEC)
• Support of five formats: mode 0, mode 1, mode 2, mode 2 form 1, and
mode 2 form 2
• Sync codes detection and protection
 Protection: When a sync code is not detected, it is automatically
inserted
• Descrambling
• ECC
 P, Q, PQ, and QP correction
 PQ or QP correction can be repeated up to three times
• EDC
Performed before and after ECC
• Mode and form are automatically detected
• Link sectors are automatically detected
• Buffering data control
Buffering CD-ROM data including SYNC code in specified format, after
the data is descrambled, corrected by ECC and checked by EDC.
I/O ports
A/D converter (ADC)
• 109 I/Os and 14 inputs
• Input or output can be selected for each bit
• 10-bit resolution
• Eight input channels
• A/D conversion request by the external trigger or timer trigger
D/A converter (DAC) • 8-bit resolution
• Two output channels
User break controller • Two break channels
(UBC)
• Addresses, data values, type of access, and data size can all be set
as break conditions
User debugging
interface (H-UDI)
Advanced user
debugger II (AUD-II)
• E10A emulator support
• JTAG-standard pin assignment
• Eight I/O pins
• Functions to read/write modules connected to internal/external buses
(except cache and H-UDI) in RAM monitor mode
On-chip RAM
• 32-Kbyte memory
Power supply voltage • PVcc, VccR, and PLLVcc: 3.0 to 3.6 V
Packages
• LQFP2424-176Cu (0.5 pitch)
Rev. 2.00 Sep. 07, 2007 Page 9 of 1312
REJ09B0320-0200