SH7261 Datasheet, PDF (204/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
7.3.5 Break Bus Cycle Register (BBR)
BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break
interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C bus
cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as
the break conditions. BBR is initialized to H'0000 by a power-on reset and in deep standby, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit: 15

Initial value: 0
R/W: R
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
 UBID DBE
CP[3:0]
CD[1:0]
ID[1:0]
RW[1:0]
SZ[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15, 14
Bit Name

13
UBID
12
DBE
11 to 8 CP[3:0]
Initial
Value
All 0
0
0
0000
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W User Break Interrupt Disable
Disables or enables user break interrupt requests
when a break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
R/W Data Break Enable
Selects whether the data bus condition is included in
the break conditions.
0: Data bus condition is not included in break
conditions
1: Data bus condition is included in break conditions
R/W I-Bus Bus Select
Select the bus master when the bus cycle of the break
condition is the I bus cycle. However, when the C bus
cycle is selected, this bit is invalidated (only the CPU
cycle).
xxx1: CPU cycle is included in break conditions
xx1x: Reserved. Setting prohibited
x1xx: Reserved. Setting prohibited
1xxx: Reserved. Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 172 of 1312
REJ09B0320-0200