SH7261 Datasheet, PDF (49/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Classification
Interrupts
Address bus
Data bus
Bus control
Symbol
I/O
NMI
I
IRQ7 to IRQ0 I
PINT7 to PINT0 I
A27 to A0
O
D31 to D0
I/O
CS6 to CS0 O
RD
O
WAIT
I
WR0
O
WR1
O
WR2
O
WR3
O
Name
Function
Non-maskable Non-maskable interrupt request pin.
interrupt
Fix it high when not in use.
Interrupt requests Maskable interrupt request pins.
7 to 0
Level-input or edge-input detection
can be selected. When the edge-
input detection is selected, the rising
edge, falling edge, or both edges can
also be selected.
Interrupt requests Maskable interrupt request pins.
7 to 0
Only level-input detection can be
selected.
Address bus
Addresses are output on these pins.
Data bus
Bidirectional data bus
Chip select 6 to 0 Chip-select signals for external
memory or devices
Read
Indicates that data is read from an
external device.
Wait
Input pin for inserting a wait cycle
into the bus cycles during access to
the external space
Byte select
Indicates a write access to bits 7 to 0
of data of external memory or
device. (For an access in units of 8,
16, or 32 bits)
Byte select
Indicates a write access to bits 15 to
8 of data of external memory or
device. (For an access in units of 16
or 32 bits)
Byte select
Indicates a write access to bits 23 to
16 of data of external memory or
device. (For an access in units of 32
bits)
Byte select
Indicates a write access to bits 31 to
24 of data of external memory or
device. (For an access in units of 32
bits)
Rev. 2.00 Sep. 07, 2007 Page 17 of 1312
REJ09B0320-0200