SH7261 Datasheet, PDF (813/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
3
MUEN
0
R/W Mute Enable
0: Module is not muted.
1: Module is muted.
2

0
R
Reserved
The read value is undefined. The write value should
always be 0.
1
TRMD
0
R/W Transmit/Receive Mode Select
0: Module is in receive mode.
1: Module is in transmit mode.
0
EN
0
R/W SSI Module Enable
0: Module is disabled.
1: Module is enabled.
18.3.2 Status Register (SSISR)
SSISR consists of status flags indicating the operational status of the SSI module and bits
indicating the current channel numbers and word numbers.
SSISR is initialized to H'02000003 by a power-on reset or in deep standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — DMRQ UIRQ OIRQ IIRQ DIRQ — — — — — — — —
Initial value: 0
0
0
0
0
0
1*² 0 — — — — — — — —
R/W: R R R R R/W*¹ R/W*¹ R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — — — — CHNO[1:0] SWNO IDST
Initial value: — — — — — — — — — — — — 0
0
1
1*²
R/W: R R R R R R R R R R R R R R R R
Notes: 1. This bit can be read from or written to. Writing 0 initializes the bit, but writing 1 is ignored.
2. The SSI clock must be kept supplied until the SSI is in the idle state.
Rev. 2.00 Sep. 07, 2007 Page 781 of 1312
REJ09B0320-0200