SH7261 Datasheet, PDF (777/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
Initial
Bit
Bit Name Value R/W Description
0
ADZ
0
R/W General Call Address Recognition Flag
This bit is valid in slave receive mode with the I²C bus
format.
[Clearing condition]
• When 0 is written in ADZ after reading ADZ = 1
[Setting condition]
• When the general call address is detected in slave
receive mode
17.3.6 Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that selects the communications format and sets the
slave address. In slave mode with the I²C bus format, if the upper seven bits of SAR match the
upper seven bits of the first frame received after a start condition, this module operates as the slave
device.
SAR is initialized to H'00 by a power-on reset or deep standby mode.
Bit: 7
6
5
4
3
2
1
0
SVA[6:0]
FS
Initial value: ₀
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7 to 1
Bit Name
SVA[6:0]
0
FS
Initial
Value R/W
0000000 R/W
0
R/W
Description
Slave Address
These bits set a unique address in these bits,
differing form the addresses of other slave devices
connected to the I²C bus.
Format Select
0: I²C bus format is selected
1: Clocked synchronous serial format is selected
Rev. 2.00 Sep. 07, 2007 Page 745 of 1312
REJ09B0320-0200