SH7261 Datasheet, PDF (1181/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
• Canceling with an interrupt
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling
edge or rising edge of an IRQ pin (IRQ7 to IRQ0: PE7 to PE4 and PC25 to PC22) (selected by
the IRQn sense select bits (IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the
interrupt controller (INTC)) is detected, clock oscillation is started after the wait time for the
oscillation settling time. This clock pulse is supplied only to the oscillation settling counter
(DSCNT) used to count the oscillation settling time.
After the elapse of the time set in the clock select bits (CKS[2:0]) in DSCNT before the
transition to deep standby mode, an overflow occurs. Since this overflow indicates that the
clock has been stabilized, the clock pulse will be supplied to the entire chip after this overflow.
Deep standby mode is thus cleared and reset exception handling is started.
When canceling deep standby mode by the NMI interrupt or IRQ interrupt, set the CKS[2:0]
bits so that the overflow period will be equal to or longer than the oscillation settling time.
The clock output phase of the CKIO pin may be unstable immediately after detecting an
interrupt and until deep standby mode is canceled. When deep standby mode is canceled by the
falling edge of the NMI pin, the NMI pin should be high when the CPU enters deep standby
mode (when the clock pulse stops) and should be low when the CPU returns from deep
standby mode (when the clock is initiated after the oscillation settling). When deep standby
mode is canceled by the rising edge of the NMI pin, the NMI pin should be low when the CPU
enters deep standby mode (when the clock pulse stops) and should be high when the CPU
returns from deep standby mode (when the clock is initiated after the oscillation settling). (This
is the same with the IRQ pin.)
• Canceling with a reset
When the RES or MRES pin is driven low, this LSI enters the power-on reset state and deep
standby mode is canceled.
Keep the RES or MRES pin low until the clock oscillation settles. When deep standby mode is
canceled by the RES pin, the contents in the on-chip RAM area are not retained.
Rev. 2.00 Sep. 07, 2007 Page 1149 of 1312
REJ09B0320-0200