SH7261 Datasheet, PDF (1320/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 31 Electrical Characteristics
31.3.16 AUD-II Timing
Table 31.20 AUD-II Timing
Conditions: PV_CC = V_CCR = PLLV_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V,
PV_CC − 0.3 V ≤ AV_CC ≤ PV_CC, AV_ref = 3.0 V to AV_CC,
PV_SS = V_SSR = PLLV_SS = AV_SS = 0 V
Item
AUDRST pulse width
AUDMD setup time
RAM monitor clock cycle
RAM monitor clock low pulse width
RAM monitor clock high pulse width
RAM monitor output data delay time
RAM monitor input data setup time
RAM monitor input data hold time
RAM monitor SYNC setup time
RAM monitor SYNC hold time
Symbol
t_AUDRSTW
t
AUDMDS
t
RMCYC
t
RMCKWL
t
RMCKWH
t_RMDD
t
RMDS
t_RMDH
t_RMSS
t_RMSH
Min.
5
5
33.33
0.4
0.4
2
15
5
15
5
Max.



0.6
0.6
14




Unit
t_RMCYC
t
RMCYC
ns
t
RMCYC
t
RMCYC
ns
ns
ns
ns
ns
Figure
Figure 31.46
Figure 31.47
AUDCK
(input)
AUDRST
AUDMD
t_RMCYC
t_AUDRSTW
t_AUDMDS
Figure 31.46 AUD Reset Timing
Rev. 2.00 Sep. 07, 2007 Page 1288 of 1312
REJ09B0320-0200