SH7261 Datasheet, PDF (22/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

17.6 Bit Synchronous Circuit..................................................................................................... 767
17.7 Usage Note......................................................................................................................... 770
17.7.1 Issuance of Stop Condition and Start Condition (Retransmission)....................... 770
17.7.2 Settings for Multi-Master Operation..................................................................... 770
17.7.3 Reading ICDRR in Master Receive Mode............................................................ 770
Section 18 Serial Sound Interface (SSI)............................................................ 771
18.1 Features.............................................................................................................................. 771
18.2 Input/Output Pins............................................................................................................... 773
18.3 Register Description .......................................................................................................... 774
18.3.1 Control Register (SSICR) ..................................................................................... 775
18.3.2 Status Register (SSISR) ........................................................................................ 781
18.3.3 Transmit Data Register (SSITDR)........................................................................ 786
18.3.4 Receive Data Register (SSIRDR) ......................................................................... 786
18.4 Operation Description........................................................................................................ 787
18.4.1 Bus Format ........................................................................................................... 787
18.4.2 Non-Compressed Modes....................................................................................... 788
18.4.3 Operation Modes .................................................................................................. 798
18.4.4 Transmit Operation............................................................................................... 799
18.4.5 Receive Operation ................................................................................................ 802
18.4.6 Temporary Stop and Restart Procedures in Transmit Mode ................................. 805
18.4.7 Serial Bit Clock Control ....................................................................................... 806
18.5 Usage Notes ....................................................................................................................... 806
18.5.1 Limitations from Overflow during Receive DMA Operation............................... 806
18.5.2 Note on Using Oversample Clock ........................................................................ 807
18.5.3 Restriction on Stopping Clock Supply.................................................................. 807
Section 19 Controller Area Network (RCAN-ET) [R5S72611]
[R5S72613]...................................................................................... 809
19.1 Summary............................................................................................................................ 809
19.1.1 Overview .............................................................................................................. 809
19.1.2 Scope .................................................................................................................... 809
19.1.3 Audience............................................................................................................... 809
19.1.4 References ............................................................................................................ 810
19.1.5 Features................................................................................................................. 810
19.2 Architecture ....................................................................................................................... 811
19.2.1 Block Diagram...................................................................................................... 811
19.2.2 Functions of Each Block....................................................................................... 812
19.2.3 Input/Output Pins.................................................................................................. 813
19.2.4 Memory Map ........................................................................................................ 814
Rev. 2.00 Sep. 07, 2007 Page xxii of xxxii