SH7261 Datasheet, PDF (843/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.2 Architecture
19.2.1 Block Diagram
The RCAN-ET device offers a flexible and sophisticated way to organise and control CAN
frames, providing the compliance to CAN2.0B Active and ISO-11898-1. The module is formed
from 5 different functional entities. These are the Micro Processor Interface (MPI), Mailbox,
Mailbox Control and CAN Interface. The figure below shows the block diagram of the RCAN-ET
Module. The bus interface timing is designed according to the peripheral bus I/F required for each
product.
CAN Interface
BCR
CRx
CTx
REC
Can Core
Transmit Buffer
Receive Buffer
TEC
Control
Signals
Status
Signals
16-bit
peripheral bus
Micro Processor
Interface
(MPI)
MCR
IRR
GSR
IMR
TXPR
TXACK
TXCR
ABACK
RXPR
RFPR
MBIMR
UMSR
Mailbox Control
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
Mailbox 0 to 15 (RAM)
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
Mailbox 0 to 15 (register)
Figure 19.1 RCAN-ET Architecture
control0
LAFM
DATA
control1
Rev. 2.00 Sep. 07, 2007 Page 811 of 1312
REJ09B0320-0200