SH7261 Datasheet, PDF (977/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.2 Block Diagrams
Figure 21.2 is a block diagram of the CD-ROM decoder functions of this LSI and the bus bridge
for connection to the peripheral bus, that is, of the elements required to implement the CD-ROM
decoder function.
SH-2A CPU
Peripheral bus controller
Stream data
Bus bridge (peripheral bus ⇔ ROM-DEC bus)
Register data
Stream data
EDC
Memory
(2 buffers for ECC)
EDC
Descrambler
Sync code
detection/
maintenance
Mode
determination
Syndrome
calculator
Memory
control
ECC control
Timing
generation
Core of CD-ROM decoder
INTC interrupt and DMAC activation control
INTC DMAC
Figure 21.2 ROM-DEC Block Diagram
The core of the CD-ROM decoder executes a series of processing required for CD-ROM
decoding, including descrambling, sync code detection, ECC correction (P- and Q-parity-based
correction), and EDC checking. The core includes sufficient memory to hold two sectors.
Rev. 2.00 Sep. 07, 2007 Page 945 of 1312
REJ09B0320-0200