SH7261 Datasheet, PDF (971/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.7 Interrupt Sources
IEB interrupt sources include the following:
• Transmit start (TXS)
• Transmit normal completion (TXF)
• Arbitration loss (TXEAL)
• Transmit timing error (TXETTME)
• Overflow of the maximum number of transmit bytes in one frame (TXERO)
• Acknowledge bits (TXEACK)
• Receive busy (RXBSY)
• Receive start (RXS)
• Receive normal completion (RXF)
• Broadcast Receive Error (RXEDE)
• Receive overrun flag (RXEOVE)
• Receive timing error (RXERTME)
• Overflow of the maximum number of receive bytes in one frame (RXEDLE)
• Parity error (RXEPE)
Each source has bits corresponding to the IEBus transmit interrupt enable register (IEIET) and the
IEBus receive interrupt enable register (IEIER) and can enable/disable interrupts. Each source also
has status flags corresponding to the IEBus transmit status register (IETSR) and IEBus receive
status register (IERSR). Reading the status flags enables determination of the interrupt sources.
Figure 20.17 shows the relations between the IEB interrupt sources.
Rev. 2.00 Sep. 07, 2007 Page 939 of 1312
REJ09B0320-0200