SH7261 Datasheet, PDF (158/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.3.3 Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to
IRQ0 individually: low level, falling edge, rising edge, or both edges. ICR1 is initialized by a
power-on reset or in deep standby mode.
Bit: 15
IRQ7
1S
Initial value: 0
R/W: R/W
14
IRQ7
0S
0
R/W
13
IRQ6
1S
0
R/W
12
IRQ6
0S
0
R/W
11
IRQ5
1S
0
R/W
10
IRQ5
0S
0
R/W
9
IRQ4
1S
0
R/W
8
IRQ4
0S
0
R/W
7
IRQ3
1S
0
R/W
6
IRQ3
0S
0
R/W
5
IRQ2
1S
0
R/W
4
IRQ2
0S
0
R/W
3
IRQ1
1S
0
R/W
2
IRQ1
0S
0
R/W
1
IRQ0
1S
0
R/W
0
IRQ0
0S
0
R/W
Bit
Bit Name
15
IRQ71S
14
IRQ70S
13
IRQ61S
12
IRQ60S
11
IRQ51S
10
IRQ50S
9
IRQ41S
8
IRQ40S
7
IRQ31S
6
IRQ30S
5
IRQ21S
4
IRQ20S
3
IRQ11S
2
IRQ10S
1
IRQ01S
0
IRQ00S
[Legend]
n = 7 to 0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W Description
R/W IRQ Sense Select
R/W These bits select whether interrupt signals
R/W
corresponding to pins IRQ7 to IRQ0 are detected by a
low level, falling edge, rising edge, or both edges.
R/W _{00: Interrupt request is detected on low level of IRQn}
R/W
input
R/W 01: Interrupt request is detected on falling edge of IRQn
R/W
input
R/W ^{10: Interrupt request is detected on rising edge of IRQn}
input
R/W _{11: Interrupt request is detected on both edges of IRQn}
R/W
input
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 2.00 Sep. 07, 2007 Page 126 of 1312
REJ09B0320-0200