SH7261 Datasheet, PDF (376/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.15 DMA Arbitration Status Register (DMASTS)
DMASTS verifies the status of DMA transfer on each channel. Writing 0 to the DASTS bit is
invalid and 1 written to the bit is not retained.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DASTS
————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Rev. 2.00 Sep. 07, 2007 Page 344 of 1312
REJ09B0320-0200