SH7261 Datasheet, PDF (892/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Figure 19.8 - Halt Mode/Sleep Mode shows allowed state transition.
• Don't set MCR5 (Sleep Mode) without entering Halt Mode.
• After setting MCR1, make sure that GSR4 is set and the RCAN-ET has entered Halt Mode
before clearing MCR1.
Power On/SW Reset
Clear MCR1
and MCR5
Set MCR1*³
Reset
clear MCR0
and GSR3 = 0
Transmission
Reception
Clear MCR5*¹
Halt Request
Clear MCR5
Set MCR1*⁴
Except Transmitter/Receiver/BusOff, if MCR6 = 0
BusOff or except Transmitter/Receiver, if MCR6 = 1
Halt Mode
Set MCR5
Clear MCR1*²
Sleep Mode
Notes:
1. MCR5 can be cleared by automatically by detecting a dominant bit on the CAN Bus if MCR7
is set or by writing "0".
2. MCR1 is cleared in SW. Clearing MCR1 and setting MCR5 have to be carried out by the
same instruction.
3. MCR1 must not be cleared in SW, before GSR4 is set. MCR1 can be set automatically in HW
when RCAN-ET moves to Bus Off and MCR14 and MCR6 are both set.
4. When MCR5 is cleared and MCR1 is set at the same time, RCAN-ET moves to Halt Request.
Right after that, it moves to Halt Mode with no reception/transmission.
Figure 19.8 Halt Mode/Sleep Mode
Rev. 2.00 Sep. 07, 2007 Page 860 of 1312
REJ09B0320-0200