SH7261 Datasheet, PDF (954/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
Initial
Bit
Bit Name Value R/W Description
0
RXEPE
0
R/(W)* Parity Error
Indicates that a parity error has occurred during data
field reception. If a parity error occurs before data field
reception, the IEB immediately enters the wait state
and the RXEPE flag is not set.
If a parity error occurs when the maximum number of
receive bytes in one frame have not been received, the
RXEPE flag is not set yet. When a parity error occurs,
the IEB returns a NAK to the communications
destination unit via the acknowledge bit. In this case,
the communications destination unit continues
retransfer up to the maximum number of receive bytes
in one frame and if the reception has been completed
normally by clearing the parity error, the RXEPE flag is
not set. If the parity error is not cleared when the
reception is terminated before receiving data for the
number of bytes specified by the message length, the
RXEPE flag is set.
In broadcast reception, if a parity error occurs during
data field reception, the IEB enters the wait state
immediately after setting the RXEPE flag. This flag is
enabled only after the receive start flag (RXS) is set. If
this error occurs before the receive start flag is set, the
IEB stops communication and enters the wait state.
This bit is not set in this case.
[Setting condition]
• When the parity bit of the last data of the data field
is not correct after the maximum number of receive
bytes have been received
[Clearing condition]
• When 1 is written
Note: * only 1 can be written to clear the flag.
Rev. 2.00 Sep. 07, 2007 Page 922 of 1312
REJ09B0320-0200