SH7261 Datasheet, PDF (871/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Bit 8 - Mailbox Empty Interrupt Flag (IRR8): This bit is set when one of the messages set for
transmission has been successfully sent (corresponding TXACK flag is set) or has been
successfully aborted (corresponding ABACK flag is set). The related TXPR is also cleared and
this mailbox is now ready to accept a new message data for the next transmission. In effect, this
bit is set by an OR'ed signal of the TXACK and ABACK bits not masked by the corresponding
MBIMR flag. Therefore, this bit is automatically cleared when all the TXACK and ABACK bits
are cleared. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR.
Writing to this bit position has no effect.
Bit 8: IRR8
0
1
Description
Messages set for transmission or transmission cancellation request NOT
progressed. (Initial value)
[Clearing Condition] All the TXACK and ABACK bits are cleared/setting
MBIMR for all TXACK and ABACK set
Message has been transmitted or aborted, and new message can be stored
[Setting condition]
When one of the TXPR bits is cleared by completion of transmission or
completion of transmission abort, i.e., when a TXACK or ABACK bit is set
(if MBIMR = 0).
Bit 7 - Overload Frame (IRR7): Flag indicating that the RCAN-ET has detected a condition that
should initiate the transmission of an overload frame. Note that on the condition of transmission
being prevented, such as listen only mode, an Overload Frame will NOT be transmitted, but IRR7
will still be set. IRR7 remains asserted until reset by writing a '1' to this bit position - writing a '0'
has no effect.
Bit 7: IRR7
0
1
Description
[Clearing condition] Writing 1 (Initial value)
[Setting conditions] Overload condition detected
Rev. 2.00 Sep. 07, 2007 Page 839 of 1312
REJ09B0320-0200