SH7261 Datasheet, PDF (1171/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
27.2.9 Deep Standby Oscillation Settling Clock Select Register (DSCNT)
DSCNT is an 8-bit readable/writable register that selects the clock used to count the oscillation
settling time when the system returns from deep standby mode. DSCNT is initialized to H'00 by a
power-on reset or in deep standby mode but retains its previous value by a manual reset or in
software standby mode. Only byte access is valid.
Since the frequency control register for the CPG (FRQCR) is initialized in deep standby mode, the
frequency of the peripheral clock (Pφ) specified by the CKS[2:0] bits in DSCNT is determined by
the FRQCR's initial value.
Bit: 7
6
5
4
3
2
1
0

CKS[2:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 3 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2 to 0 CKS[2:0] 000
R/W Clock Select
Selects the clock used to count the oscillation settling
time from among eight types clocks derived by
dividing the peripheral clock (Pφ).
The oscillation settling time is calculated as follows:
Oscillation settling time = 1/Pφ × Division ratio
specified by CKS[2:0] × 255 [µs]
The following are the oscillation settling times when
the peripheral clock (Pφ) is running at 5, 10, and 15
MHz.
Setting Clock
value select
Oscillation settling time (ms)
5 MHz
10 MHz
15 MHz
000: 1 × Pφ*¹
0.05
0.03
0.02
001: 1/64 × Pφ*¹ 3.26
1.63
1.09
010: 1/128 × Pφ*¹ 6.53
3.26
2.18
011: 1/256 × Pφ*² 13.06
6.53
4.35
100: 1/512 × Pφ*² 26.11
13.06
8.70
101: 1/1024 × Pφ 52.22
26.11
17.41
110: 1/4096 × Pφ 208.90
104.45
69.63
111: 1/16384 × Pφ 835.58
417.79
278.53
Notes: 1. Do not use this setting.
2. Set the clock so that it is equal to or longer than the oscillation settling time 2 on return
from standby (t ).
OSC3
Rev. 2.00 Sep. 07, 2007 Page 1139 of 1312
REJ09B0320-0200