SH7261 Datasheet, PDF (195/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.9 Data Transfer with Interrupt Request Signals
Interrupt request signals can be used to activate the DMAC and transfer data.
Interrupt sources that are specified to activate the DMAC are masked by setting the DMA transfer
enable bit in DREQER0 to DREQER3 to 1 without being input to the INTC.
6.9.1
Handling Interrupt Request Signals as Sources for CPU Interrupt but not DMAC
Activation
1. Clear the corresponding DMAC transfer request enable bit in DREQER0 to DREQER3 to 0.
2. When an interrupt occurs, the interrupt request will be sent to the CPU.
3. The CPU clears the interrupt source and performs the necessary processing in the interrupt
handling routine.
6.9.2
Handling Interrupt Request Signals as Sources for DMAC Activation but not CPU
Interrupt
1. Select* the signals as DMAC activating sources by setting the corresponding DMAC transfer
request enable bit in DREQER0 to DREQER3 to 1. This masks the CPU interrupt source
regardless of the interrupt priority register settings.
2. When an interrupt occurs, the activation source will be sent to the DMAC.
3. The DMAC clears the activation source during the transfer.
Note: * As for the method to select the DMAC request sources, see section 11, Direct Memory
Access Controller (DMAC).
Rev. 2.00 Sep. 07, 2007 Page 163 of 1312
REJ09B0320-0200