SH7261 Datasheet, PDF (991/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Initial
Bit Bit Name Value
R/W Description
4
ER0SEL 0
R/W CD-ROM Data-Related Status Register Setting
Condition
0: Information is on the sector being decoded.
1: Information is on the latest sector that has been
buffered.
This condition affects the information given by bits 5 to
0 in the CROMST0 register, bits 7 to 1 in the
CROMST4 and CROMST5 registers, and HEAD00 to
HEAD02.
3
NO_ECC 0
R/W ECC correction mode when the result of the EDC check
before ECC correction was 'pass'
When this bit is set to 1, ECC correction is not
performed if the result of pre-correction EDC checking
is a 'pass', regardless of the results of syndrome
calculation.
2 to 0 
All 0
R/W Reserved
These bits are always read as 0. The write value should
always be 0.
Note: The setting of this register is reapplied on each sector-to-sector transition.
21.3.7 HEAD20 to HEAD22 Representation Control Register (CROMCTL5)
CROMCTL5 specifies the representation mode for HEAD20 to HEAD22.
Bit: 7
—
Initial value: 0
R/W: R/W
6
—
0
R/W
5
—
0
R/W
4
—
0
R/W
3
—
0
R/W
2
—
0
R/W
10
—
MSF_
LBA_SEL
00
R/W R/W
Bit Bit Name
7 to 1 
Initial
Value
All 0
0
MSF_LBA_ 0
SEL
R/W Description
R/W Reserved
These bits are always read as 0. The write value should
always be 0.
R/W HEAD20 to HEAD22 Representation Mode
0: BCD M, F, and S values in the header as is
1: Total sector number in HEX
Rev. 2.00 Sep. 07, 2007 Page 959 of 1312
REJ09B0320-0200