SH7261 Datasheet, PDF (112/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
(7) Frequency Control Register (FRQCR)
The frequency control register (FRQCR) has control bits assigned for the following functions:
clock output/non-output from the CKIO pin during software standby mode, the frequency
multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the
peripheral clock (Pφ).
(8) Standby Control Register
The standby control register has bits for controlling the power-down modes. See section 27,
Power-Down Modes, for more information.
4.2 Input/Output Pins
Table 4.1 lists the clock pulse generator pins and their functions.
Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator
Pin Name
Symbol
Mode control pins MD_CLK0
MD_CLK1
Crystal
XTAL
input/output pins
(clock input pins)
EXTAL
Clock input/output CKIO
pin
I/O
Input
Input
Output
Input
I/O
Function
(Clock Operating
Modes 0 and 2)
Sets the clock operating
mode.
Sets the clock operating
mode.
Connected to the crystal
resonator. (Leave this pin
open when the crystal
resonator is not in use.)
Connected to the crystal
resonator or used to input
an external clock.
Clock output pin.
Function
(Clock Operating
Mode 3)
Sets the clock operating
mode.
Sets the clock operating
mode.
Leave this pin open.
Pull-up this pin.
Clock input pin.
Rev. 2.00 Sep. 07, 2007 Page 80 of 1312
REJ09B0320-0200