SH7261 Datasheet, PDF (66/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.3.2 Addressing Modes
Addressing modes and effective address calculation are as follows:
Table 2.8 Addressing Modes and Effective Addresses
Addressing Mode Instruction Format Effective Address Calculation
Equation
Register direct
Rn
The effective address is register Rn.
—
(The operand is the contents of register Rn.)
Register indirect @Rn
The effective address is the contents of register Rn
Rn.
Rn
Rn
Register indirect @Rn+
with post-increment
The effective address is the contents of register Rn
Rn. A constant is added to the contents of Rn _{(After instruction}
after the instruction is executed. 1 is added for a _execution)
byte operation, 2 for a word operation, and 4 for
a longword operation.
Byte:
Rn + 1 → Rn
Rn
Rn
Rn + 1/2/4 ₊
Word:
Rn + 2 → Rn
1/2/4
Longword:
Rn + 4 → Rn
Register indirect @-Rn
with pre-decrement
The effective address is the value obtained by Byte:
subtracting a constant from Rn. 1 is subtracted Rn – 1 → Rn
for a byte operation, 2 for a word operation, and _Word:
4 for a longword operation.
Rn – 2 → Rn
Rn
Rn – 1/2/4 _–
Rn – 1/2/4
Longword:
Rn – 4 → Rn
(Instruction is
1/2/4
executed with
Rn after this
calculation)
Rev. 2.00 Sep. 07, 2007 Page 34 of 1312
REJ09B0320-0200