SH7261 Datasheet, PDF (1176/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer
control/status register (WTCSR) of the WDT before the transition to software standby mode,
the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the
clock pulse will be supplied to the entire chip after this overflow. Software standby mode is
thus cleared and NMI interrupt exception handling (IRQ interrupt exception handling in case
of IRQ) is started. However, when the IRQ interrupt priority level is lower than the interrupt
mask level set in the status register (SR) of the CPU, the interrupt request is not accepted and
software standby mode is not canceled.
When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the
CKS[2:0] bits so that the WDT overflow period will be equal to or longer than the oscillation
settling time.
The clock output phase of the CKIO pin may be unstable immediately after detecting an
interrupt and until software standby mode is canceled. When software standby mode is
canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters
software standby mode (when the clock pulse stops) and should be low when the CPU returns
from software standby mode (when the clock is initiated after the oscillation settling). When
software standby mode is canceled by the rising edge of the NMI pin, the NMI pin should be
low when the CPU enters software standby mode (when the clock pulse stops) and should be
high when the CPU returns from software standby mode (when the clock is initiated after the
oscillation settling) (This is the same with the IRQ pin.)
• Canceling with a reset
When the RES pin is driven low, software standby mode is canceled and the LSI enters the
power-on reset state. After that, if the RES pin is driven high, the power-on reset exception
handling is started.
When the MRES pin is driven low, software standby mode is canceled and the LSI enters the
manual reset state. After that, if the MRES pin is driven high, the manual reset exception
handling is started.
Keep the RES or MRES pin low until the clock oscillation settles. The internal clock will
continue to be output to the CKIO pin in clock mode 0 or 2.
(3) Note on Making a Transition To Software Standby Mode
If the SLEEP instruction is executed to make a transition to software standby mode during transfer
by the DMAC, the DMAC stops its operation without waiting for the completion of the transfer.
Thus, the DMA transfer is not guaranteed. Therefore, when making a transition to software
standby mode, wait for the completion of the DMA transfer or stop the DMA transfer to execute
the SLEEP instruction.
Rev. 2.00 Sep. 07, 2007 Page 1144 of 1312
REJ09B0320-0200