SH7261 Datasheet, PDF (562/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(b) Basic Operation Example of A/D Converter Start Request Delaying Function
Figure 12.74 shows a basic example of A/D converter request signal (TRG4AN) operation when
the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter start request
signal is output during TCNT_4 down-counting.
Transfer from cycle buffer
register to cycle register
Transfer from cycle buffer
register to cycle register
Transfer from cycle buffer
register to cycle register
TADCORA_4
TADCOBRA_4
TCNT_4
A/D converter
start request
(TRG4AN)
(Complementary PWM mode)
Figure 12.74 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation
(c) Buffer Transfer
The data in the timer A/D converter start request cycle set registers (TADCORA_4 and
TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set buffer
registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer registers to the
respective cycle set registers at the timing selected with the BF1 and BF0 bits in the timer A/D
converter start request control register (TADCR_4).
(d) A/D Converter Start Request Delaying Function Linked with Interrupt Skipping
A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt
skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer
A/D converter start request control register (TADCR).
Figure 12.75 shows an example of A/D converter start request signal (TRG4AN) operation when
TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D converter
start requests are linked with interrupt skipping.
Rev. 2.00 Sep. 07, 2007 Page 530 of 1312
REJ09B0320-0200