SH7261 Datasheet, PDF (960/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.4 Data Format
20.4.1 Transmission Format
Figure 20.6 shows the relationship between the transfer format and each register during the IEBus
data transmission.
[In master transmission]
Communications frame Master address
Slave address
Control bits
Message length bits
Data bits
Register
IEAR1, IEAR2
IESA1, IESA2
IEMCR
IETBFL
IETB001 to IETB128
[In slave transmission]
Communications frame ^{Master address}
Slave address
Control bits
Message length bits
Data bits
Register
(*2)
(*1)
(*3)
IEAR1, IEAR2
IETBFL
IETB001 to IETB128
Notes:
1. In slave transmission, the received master address is not saved. If the unit is locked,
address comparison performed.
2. The received slave address is compared with IEAR1 and IEAR2, and if these addresses
match, operation continues.
3. In slave transmission, the received control bits are not saved. The received control bits
are decoded to decide the subsequent operation.
Figure 20.6 Relationship between Transfer Format
and Each Register during IEBus Data Transmission
Rev. 2.00 Sep. 07, 2007 Page 928 of 1312
REJ09B0320-0200