SH7261 Datasheet, PDF (809/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
15
SCKD
0
R/W Serial Bit Clock Direction
0: Serial bit clock is input, slave mode.
1: Serial bit clock is output, master mode.
Note: SSI0 and SSI1 permit only the following setting:
(SCKD, SWSD) = (0,0) and (1,1). Other settings
are prohibited.
14
SWSD
0
R/W Serial WS Direction
0: Serial word select is input, slave mode.
1: Serial word select is output, master mode.
Note: SSI0 and SSI1 permit only the following setting:
(SCKD, SWSD) = (0,0) and (1,1). Other settings
are prohibited.
13
SCKP
0
R/W Serial Bit Clock Polarity
0: SSIWS and SSIDATA change at the SSISCK falling
edge (sampled at the SCK rising edge).
1: SSIWS and SSIDATA change at the SSISCK rising
edge (sampled at the SCK falling edge).
SCKP = 0
SCKP = 1
SSIDATA input sampling timing at
the time of reception (TRMD = 0)
SSISCK rising
edge
SSISCK falling
edge
SSIDATA output change timing at
the time of transmission (TRMD = 1)
SSISCK falling
edge
SSISCK rising
edge
SSIWS input sampling timing at
the time of slave mode (SWSD = 0)
SSISCK rising
edge
SSISCK falling
edge
SSIWS output change timing at
the time of master mode (SWSD = 1)
SSISCK falling
edge
SSISCK rising
edge
12
SWSP
0
R/W Serial WS Polarity
0: SSIWS is low for 1st channel, high for 2nd channel.
1: SSIWS is high for 1st channel, low for 2nd channel.
Rev. 2.00 Sep. 07, 2007 Page 777 of 1312
REJ09B0320-0200