SH7261 Datasheet, PDF (1014/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.43 Automatic Buffering Start Sector Setting: Seconds Control Register (CBUFCTL2)
CBUFCTL2 indicates the seconds value in the header for the first sector to be buffered.
Bit: 7
6
5
4
3
2
1
0
BS_SEC[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7 to 0
Bit Name
BS_SEC[7:0]
Initial
Value
All 0
R/W Description
R/W Setting of the seconds value in the header for the first
sector to be buffered
21.3.44 Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3)
CBUFCTL3 indicates the frames (1 frame = 1/75 second) value in the header for the first sector to
be buffered.
Bit: 7
6
5
4
3
2
1
0
BS_FRM[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7 to 0
Bit Name
BS_FRM[7:0]
Initial
Value
All 0
R/W Description
R/W Setting of the frames (1/75 second) value in the header
for the first sector to be buffered
Rev. 2.00 Sep. 07, 2007 Page 982 of 1312
REJ09B0320-0200