SH7261 Datasheet, PDF (935/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.3.6 IEBus Slave Address Setting Register 1 (IESA1)
IESA1 sets the lower four bits of the communications destination slave unit address.
IESA1 is initialized by a power-on reset or in deep standby.
Bit: 7
6
5
4
3
2
1
0
ISAL4
————
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R R R R
Initial
Bit
Bit Name Value R/W Description
7 to 4 ISAL4
0000 R/W Lower 4 Bits of IEBus Slave Address
These bits set the lower 4 bits of the communication
destination slave unit address
3 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
20.3.7 IEBus Slave Address Setting Register 2 (IESA2)
IESA2 sets the upper eight bits of the communications destination slave unit address.
IESA2 is initialized by a power-on reset or in deep standby.
Bit: 7
6
5
4
3
2
1
0
ISAU8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 0 ISAU8
All 0 R/W Upper 8 Bits of IEBus Slave Address
Set upper 8 bits of the communications destination
slave unit address
Rev. 2.00 Sep. 07, 2007 Page 903 of 1312
REJ09B0320-0200