SH7261 Datasheet, PDF (983/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Name
Abbreviation R/W
Post-ECC correction subheader:
channel number (byte 21) data register
SHEAD25
R
Post-ECC correction subheader:
sub-mode (byte 22) data register
SHEAD26
R
Post-ECC correction subheader:
data type (byte 23) data register
SHEAD27
R
Automatic buffering setting control register CBUFCTL0
R/W
Automatic buffering start sector setting:
minutes control register
CBUFCTL1
R/W
Automatic buffering start sector setting:
seconds control register
CBUFCTL2
R/W
Automatic buffering start sector setting:
frames control register
CBUFCTL3
R/W
ISY interrupt source mask control register CROMST0M R/W
CD-ROM decoder reset control register
ROMDECRST R/W
CD-ROM decoder reset status register
RSTSTAT
R/W
SSI data control register
SSI
R/W
Interrupt flag register
INTHOLD
R/W
Interrupt source mask control register
INHINT
R/W
Buffer control register
RINGBUFCTL R/W
CD-ROM decoder stream data input register STRMDIN0
R/W
CD-ROM decoder stream data input register STRMDIN1
R/W
CD-ROM decoder stream data input register STRMDIN2
R/W
CD-ROM decoder stream data input register STRMDIN3
R/W
CD-ROM decoder stream data output
register
STRMDOUT0 R/W
CD-ROM decoder stream data output
register
STRMDOUT1 R/W
Initial
Value Address
H'00 H'E800002D
H'00 H'E800002E
H'00 H'E800002F
H'04
H'00
H'E8000040
H'E8000041
H'00 H'E8000042
H'00 H'E8000043
H'00
H'00
H'00
H'18
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'E8000045
H'E8000100
H'E8000101
H'E8000102
H'E8000108
H'E8000109
H'E800010C
H'E8000200
H'E8000201
H'E8000202
H'E8000203
H'E8000204
H'00 H'E8000205
Access
Size
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Read: 16
Write: 32
16
Rev. 2.00 Sep. 07, 2007 Page 951 of 1312
REJ09B0320-0200