SH7261 Datasheet, PDF (586/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.4 Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 12.109 shows the timing in this case.
TCNT write cycle
T1 T2
Pφ
Address
Write signal
Counter clear
signal
TCNT
TCNT address
N
H'0000
Figure 12.109 Contention between TCNT Write and Clear Operations
12.7.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 12.110 shows the timing in this case.
TCNT write cycle
T1 T2
Pφ
Address
TCNT address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 12.110 Contention between TCNT Write and Increment Operations
Rev. 2.00 Sep. 07, 2007 Page 554 of 1312
REJ09B0320-0200