SH7261 Datasheet, PDF (887/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.8 Unread Message Status Register 0 (UMSR0)
This register is a 16-bit read/conditionally write register and it records the mailboxes whose
contents have not been accessed by the CPU prior to a new message being received. If the CPU
has not cleared the corresponding bit in the RXPR or RFPR when a new message for that mailbox
is received, the corresponding UMSR bit is set to '1'. This bit may be cleared by writing a '1' to the
corresponding bit location in the UMSR. Writing a '0' has no effect.
If a mailbox is configured as transmit box, the corresponding UMSR will not be set.
• UMSR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UMSR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit 15 to 0 — Indicate that an unread received message has been overwritten or overrun condition
has occurred for Mailboxes 15 to 0.
Bit[15:0]: UMSR0
0
1
Description
[Clearing Condition] Writing '1' (initial value)
Unread received message is overwritten by a new message or overrun
condition
[Setting Condition] When a new message is received before RXPR or RFPR
is cleared
Rev. 2.00 Sep. 07, 2007 Page 855 of 1312
REJ09B0320-0200