SH7261 Datasheet, PDF (1003/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.23 Pre-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD02)
SHEAD02 indicates the sub-mode value in the subheader before ECC correction (byte 18).
Bit: 7
6
5
4
3
2
1
0
SHEAD02[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit Bit Name
Initial
Value R/W Description
7 to 0 SHEAD02[7:0] All 0 R
Sub-mode value in the subheader before ECC
correction (byte 18)
For sectors not in Mode 2, this register contains the
byte of data at the corresponding position.
21.3.24 Pre-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD03)
SHEAD03 indicates the data type value in the subheader before ECC correction (byte 19).
Bit: 7
6
5
4
3
2
1
0
SHEAD03[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit Bit Name
Initial
Value R/W Description
7 to 0 SHEAD03[7:0] All 0 R
Data type value in the subheader before ECC
correction (byte 19)
For sectors not in Mode 2, this register contains the
byte of data at the corresponding position.
Rev. 2.00 Sep. 07, 2007 Page 971 of 1312
REJ09B0320-0200