SH7261 Datasheet, PDF (702/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
receive-error interrupts are requested independently.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• The quantity of data in the transmit and receive FIFO registers and the number of receive
errors of the receive data in the receive FIFO register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 16.1 shows a block diagram of the SCIF.
Module data bus
RxD
TxD
SCK
SCFRDR (16 stage)
SCRSR
SCFTDR (16 stage)
SCTSR
SCSMR
SCLSR
SCFDR
SCFCR
SCFSR
SCSCR
SCSPTR
Transmission/reception
control
SCBRR
Baud rate
generator
Parity generation
Parity check
Clock
External clock
[Legend]
SCRSR: Receive shift register
SCFRDR: Receive FIFO data register
SCTSR: Transmit shift register
SCFTDR: Transmit FIFO data register
SCSMR: Serial mode register
SCSCR: Serial control register
SCIF
SCFSR: Serial status register
SCBRR: Bit rate register
SCSPTR:Serial port register
SCFCR: FIFO control register
SCFDR: FIFO data count register
SCLSR: Line status register
Figure 16.1 Block Diagram of SCIF
Peripheral
bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
BRI
Rev. 2.00 Sep. 07, 2007 Page 670 of 1312
REJ09B0320-0200