SH7261 Datasheet, PDF (36/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Item
Interrupt controller
(INTC)
Bus state controller
(BSC)
Bus monitor
Features
• Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to
PINT0)
• On-chip peripheral interrupts: Priority level set for each module
• 16 priority levels available
• Register bank enabling fast register saving and restoring in interrupt
handling
• CSC
 Seven-channel chip select controller (CSC)
 External devices with their bus sizes of 32, 16, or 8 bits can be
connected
 Cycle wait function
Up to 31 cycles (up to 7 cycles for page access cycle)
 The following features settable for wait controlling
Timings of asserting and negating chip select signals
Timings of asserting and negating read/write signals
Timings of starting and stopping data output
 One-write strobe and byte write strobe modes are available as
write access modes
 Page read and page write modes are available as page access
modes
• SDRAMC
 Two-channel external SDRAM interfaces
 Auto refresh using the internal programmable refresh counter or
self refresh mode selectable
 The following features settable
Row-column latency, column latency, row-active period, write-
recovery period, row precharge period, auto refresh request
interval, initial precharge cycle count, and initial auto refresh
request interval
 Random column burst access available (one SDRAM burst length)
 Initialization sequencer issues precharge and auto refresh
commands
• Bus monitor function
When an illegal address access or a bus timeout is detected, a bus
error interrupt is generated.
Rev. 2.00 Sep. 07, 2007 Page 4 of 1312
REJ09B0320-0200