SH7261 Datasheet, PDF (338/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
• Interrupt request
 Two types of interrupt requests (generated when the byte count reaches "0")
• Interrupt request signals for each channel
• Interrupt request signal common to all channels
• Reload function (source address, destination address, byte count) settable
• Rotate function settable
• DMAC stop/restart/suspend function settable
Notes: Terminologies in this section are as follows:
1. Single data transfer: Transfer in one read cycle and one write cycle by the DMAC (in
the case of dual address transfer)
2. Single operand transfer: Continuous data transfer by the DMAC on one channel
(amount of data to be transferred is set in a register)
3. One DMA transfer: Transferring a number of data, from the start address to the end
address set in the byte count register
4. Channel number: n = 0 to 7
5. Request source number: k = 1 to 37, m = 0 to 37
6. BIU: Bus Interface Unit (peripheral module). One of the following four kinds according to
the source or destination of transfer.
BIU_E: External space (normal space and SDRAM space)
BIU_P: Peripheral bus (1) (see figure 1.1)
BIU_SH: Peripheral bus (2) (see figure 1.1), on-chip RAM space
BIU_C: Peripheral bus (3) (see figure 1.1)
Figure 11.1 is a block diagram of the DMAC
Rev. 2.00 Sep. 07, 2007 Page 306 of 1312
REJ09B0320-0200