SH7261 Datasheet, PDF (1154/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 Pin Function Controller (PFC)
Initial
Bit
Bit Name Value R/W Description
5, 4
PF1MD[1:0] 00
R/W PF1 Mode
These bits control the function of the PF1/
AUDMD/RxD7 pin.
00: PF1 I/O (port)
01: AUDMD input (AUD-II)
10: RxD7 input (SCIF)
11: Setting prohibited
3, 2
—
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
PF0MD[1:0] 00
R/W PF0 Mode
These bits control the function of the PF0/
AUDRST/TxD7 pin.
00: PF0 I/O (port)
01: AUDRST input (AUD-II)
10: TxD7 output (SCIF)
11: Setting prohibited
25.2 Usage Note
The settings of the port control registers are used as the output pin select signals, and are not
basically used as the input pin select signals. This causes the signals input from the pins to
propagate to all the modules having the relevant multiplexed pins. So, unnecessary input signals
must be disabled by the settings of the respective modules.
Settings of port control registers are decoded to enable/disable pins IRQ7A to IRQ0A and IRQ7B
to IRQ0B or pins PINT7A to PINT0A and PINT7B to PINT0B. Be sure to select either one of
them.
Rev. 2.00 Sep. 07, 2007 Page 1122 of 1312
REJ09B0320-0200