SH7261 Datasheet, PDF (1332/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions and Additions in this Edition
Item
11.1 Features
15.5.1 Register Writing during
RTC Count
Figure 16.11 Sample Flowchart
for Transmitting Serial Data
Page Revision (See Manual for Details)
306 Modified
1. Single data transfer: Transfer in one read cycle and one
write cycle by the DMAC (in the case of dual address
transfer), and one read cycle or one write cycle transfer by
the DMAC (at single address transfer)
2. Single operand transfer: Continuous data transfer by the
DMAC on one channel (amount of data to be transferred is
set in a register)
:
6. BIU: Bus Interface Unit (peripheral module). One of the
following four kinds according to the source or destination of
transfer.
BIU_E: External space (normal space and SDRAM
space)
BIU_P: Peripheral bus (1) (see figure 1.1)
BIU_SH: Peripheral bus (2) (see figure 1.1), on-chip
RAM space
BIU_C: Peripheral bus (3) (see figure 1.1)
665 Modified
Do not write to the count registers (RSECCNT,
RMINCNT, RHRCNT, RDAYCNT, RWKCNT,
RMONCNT, and RYRCNT) during the RTC counting
(while the START bit in RCR2 is 1). If any of the count
registers is written to during the RTC counting, the
count register may not be read correctly immediately
after the execution of a write instruction. The RTC
counting must be stopped before writing to any of the
count registers.
720 Modified
Yes
Write transmit data to SCFTDR
and read 1 from TDFE and
TEND flags in SCFSR, then clear
[1]
these flags to 0
No
All data transmitted?
[1] SCIF status check and transmit data write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, and read 1
from the TDFE and TEND flags, then
clear these flags to 0
Rev. 2.00 Sep. 07, 2007 Page 1300 of 1312
REJ09B0320-0200