SH7261 Datasheet, PDF (860/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Note:
After issuing a Halt request the CPU is not allowed to set TXPR or TXCR or clear MCR1
until the transition to Halt mode is completed (notified by IRR0 and GSR4). After MCR1
is set this can be cleared only after entering Halt mode or through a reset operation (SW or
HW).
Note: Transition into or recovery from Halt mode, is only possible if the BCR1 and BCR0
registers are configured to a proper Baud Rate.
Bit 1: MCR1
0
1
Description
Clear Halt request (Initial value)
Halt mode transition request
Bit 0 — Reset Request (MCR0): Controls resetting of the RCAN-ET module. When this bit is
changed from '0' to '1' the RCAN-ET controller enters its reset routine, re-initialising the internal
logic, which then sets GSR3 and IRR0 to notify the reset mode. During a re-initialisation, all user
registers are initialised.
RCAN-ET can be re-configured while this bit is set. This bit has to be cleared by writing a '0' to
join the CAN bus. After this bit is cleared, the RCAN-ET module waits until it detects 11
recessive bits, and then joins the CAN bus. The Baud Rate needs to be set up to a proper value in
order to sample the value on the CAN Bus.
After Power On Reset, this bit and GSR3 are always set. This means that a reset request has been
made and RCAN-ET needs to be configured.
The Reset Request is equivalent to a Power On Reset but controlled by Software.
Bit 0: MCR0
0
1
Description
Clear Reset Request
CAN Interface reset mode transition request (Initial value)
Rev. 2.00 Sep. 07, 2007 Page 828 of 1312
REJ09B0320-0200