SH7261 Datasheet, PDF (937/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.3.9 IEBus Reception Master Address Register 1 (IEMA1)
IEMA1 indicates the lower four bits of the communication destination master unit address in
slave/broadcast reception.
IEMA1 is initialized by a power-on reset or in deep standby.
Bit: 7
6
5
4
3
2
1
0
IMAL4
————
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Initial
Bit
Bit Name Value R/W Description
7 to 4 IMAL4
0000 R
Lower Four Bits of IEBus Reception Master Address
Indicates the lower four bits of the communication
destination master unit address in slave/broadcast
reception. This register is enabled when
slave/broadcast reception starts, and the contents are
changed at the time of setting the RXS flag. If a
broadcast receive error interrupt is selected by the DEE
bit in IECTR and the receive buffer is not in the receive
enabled state at control field reception, a receive error
interrupt is generated and the lower four bits of the
master address are stored in IEMA1.
3 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 905 of 1312
REJ09B0320-0200