SH7261 Datasheet, PDF (43/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
1.3 Block Diagram
The block diagram of this LSI is shown in figure 1.1.
External
bus I/O
External bus
width
mode input
SH-2A CPU
core
Floating-point
unit (FPU)
Instruction cache Operand cache
memory (8 kbytes) memory (8 kbytes)
Cache controller
On-chip
RAM
(32 kbytes)
User break
controller
(UBC)
CPU instruction fetch bus (F bus)
CPU memory access bus (M bus)
CPU bus
(C bus)
UBCTRG
output
Advanced user
debugger-II
(AUD-II)
AUDRST input
AUDSYNC input
AUDCK input
AUDMD input
AUDATA I/O
Bus bridge
Internal bus (I bus)
Internal CPU bus
Internal DMA write bus
Internal DMA read bus
Bus state
controller
(BSC)
On-chip
peripheral
module bus 1
controller
On-chip
peripheral
module bus 2
controller
Bus
monitor
Direct memory
access controller
(DMAC)
DREQ input
DACK output
DACT output
DTEND output
On-chip
peripheral
module bus 3
controller
CD-ROM
decoder
(ROM-DEC)
On-chip peripheral
module bus 1
On-chip peripheral module bus 3
On-chip peripheral module bus 2
Pin function
controller
(PFC)
I/O port
Clock pulse
generator
(CPG)
Watchdog
timer
(WDT)
Interrupt
controller
(INTC)
Multi-function
timer pulse
unit 2
(MTU2)
8-bit timer
(TMR)
Realtime
clock
(RTC)
Port
General I/O
User debugging
interface
(H-UDI)
Power-down
mode control
Port
Port
EXTAL input WDTOVF output
XTAL output
CKIO I/O
Clock mode input
Port
RES input
MRES input
NMI input
IRQ input
PINT input
Port
Port
Port
Timer pulse I/O
RTC_X1 input
RTC_X2 output
Compare match output
External counter clock input
External counter reset input
D/A
converter
(DAC)
A/D
converter
(ADC)
*²
*¹
IEBusTM
controller
(IEB)
Controller
area network
(RCAN-ET)
Serial sound
interface
(SSI)
I²C bus
interface 3
(IIC3)
Serial
communication
interface with
FIFO (SCIF)
Port
Port
JTAG I/O
Analog output
Notes: 1. R5S72611 and R5S72613 support this unit.
2. R5S72612 and R5S72613 support this unit.
Port
Analog input
ADTRG input
Port
IEB bus I/O
Port
Port
Port
CAN bus I/O Serial I/O
I²C bus I/O
Audio clock input
Port
Serial I/O
Figure 1.1 Block Diagram
Rev. 2.00 Sep. 07, 2007 Page 11 of 1312
REJ09B0320-0200