SH7261 Datasheet, PDF (963/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.5.2 Master Transmission
Figure 20.9 shows the flowchart for master transmission.
Start
Initial setting
[IESA1, IESA2 register setting]
Slave address
[IEMCR register setting]
Broadcast/normal selection
Retransfer counts
Control bits
[IETBFL register setting]
Message length bits
[IETB001 to IETB128 setting]
Transmit data
[IECMR register setting]
Master communications
request command
Transmit start interrupt
Transmit error interrupt
(TXE***)
Transmit start interrupt (TXS)
Interrupt processing
IETSR[TXS] clear
Transmit completion
interrupt
Transmit error interrupt
(TXE***)
Transmit completion interrupt (TXF)
Interrupt processing
IETSR[TXF] clear
Interrupt processing
IETSR[TXE***] clear
End
Figure 20.9 Flowchart for Master Transmission
Rev. 2.00 Sep. 07, 2007 Page 931 of 1312
REJ09B0320-0200