SH7261 Datasheet, PDF (373/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.13 DMA Interrupt Status Register (DMISTS)
DMISTS consists of the DMA interrupt request status bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DISTS
————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value
R/W Description
31 to 24 DISTS
All 0
R
DMA Interrupt Request Status
These bits are used to verify the sources of common
interrupt requests for the interrupt controller.
• Condition for setting to "1"
When the DMA common interrupt request signal
control bit (DINTA) for a channel is set to "1" and
the DMA transfer end condition is detected, the
corresponding bit is set to "1". The setting of the
DMA interrupt control bit (DINTM) does not affect
this setting.
• Condition for clearing to "0"
A DISTS bit is cleared to "0" by clearing the
corresponding DMA transfer end condition
detection bit (DEDET) in the DMA transfer end
detection register (DMEDET). For details, see
section 11.5.2, DMA Interrupt Requests.
0: No interrupt request
1: An interrupt request exists
23 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Notes: 1. This register is read-only.
2. Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel
1, …, 24: channel 7).
Rev. 2.00 Sep. 07, 2007 Page 341 of 1312
REJ09B0320-0200