SH7261 Datasheet, PDF (652/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
13.7.2 A/D Converter Activation
The A/D converter can be activated only by TMR_0 compare match A.
If the ADTE bit in TCSR_0 is set to 1 when the CMFA flag in TCSR_0 is set to 1 by the
occurrence of TMR_0 compare match A, a request to start A/D conversion is sent to the A/D
converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at
this time, A/D conversion is started.
13.8 Usage Notes
13.8.1 Notes on Setting Cycle
If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in
which the values of TCNT and TCOR match. TCNT updates the counter value at this last state.
Therefore, the counter frequency is obtained by the following formula.
f = Pφ/(N + 1)
f: Counter frequency
Pφ:Operating frequency
N: TCOR value
13.8.2 Conflict between TCNT Write and Clear
If a counter clear signal is generated during the T₂ state of a TCNT write cycle, the clear takes
priority and the write is not performed as shown in figure 13.12.
Pφ
Address
TCNT write cycle by CPU
T₁
T₂
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 13.12 Conflict between TCNT Write and Clear
Rev. 2.00 Sep. 07, 2007 Page 620 of 1312
REJ09B0320-0200