SH7261 Datasheet, PDF (1061/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

(1)
Pφ
Section 22 A/D Converter (ADC)
Address
(2)
Write
signal
Input sampling
timing
ADIF
t_D
t_SPL
t_CONV
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t_D: A/D conversion start delay time
t_SPL: Input sampling time
t_CONV: A/D conversion time
Figure 22.5 A/D Conversion Timing
Table 22.4 A/D Conversion Time (Single Mode)
CKS1 = 0
CKS0 = 0
CKS0 = 1
Item
Symbol Min. Typ. Max. Min. Typ. Max.
A/D conversion t_D
start delay time
11
—
14
19
—
26
Input sampling
t_SPL
time
—
33
—
—
65
—
A/D conversion t_CONV
time
135 —
138 267 —
274
Note: Values in the table are the numbers of states.
CKS1 = 1
CKS0 = 0
Min. Typ. Max.
35
—
50
—
129 —
531 —
546
Rev. 2.00 Sep. 07, 2007 Page 1029 of 1312
REJ09B0320-0200