SH7261 Datasheet, PDF (646/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
13.4.2 Reset Input
Figure 13.3 shows an example of the 8-bit timer being used to generate a pulse which is output
after a desired delay time from a TMRI input. The control bits are set as follows:
1. Set both bits CCLR1 and CCLR0 in TCR to 1 and set the TMRIS bit in TCCR to 1 so that
TCNT is cleared at the high level input of the TMRI signal.
2. In TCSR, set bits OS3 to OS0 to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides pulses output at a desired delay time from a TMRI
input determined by TCORA and with a pulse width determined by TCORB and TCORA.
TCORB
TCORA
H'00
TMRI
TMO
TCNT
Figure 13.3 Example of Reset Input
Rev. 2.00 Sep. 07, 2007 Page 614 of 1312
REJ09B0320-0200