SH7261 Datasheet, PDF (168/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.3.13 DMA Transfer Request Enable Register 3 (DREQER3)
DMA transfer request enable register 3 (DREQER3) is an 8-bit readable/writable register that
enables/disables the ADC, MTU2 (channels 0 to 4), and RCAN-ET (channels 0 and 1) DMA
transfer requests, and enables/disables CPU interrupt requests.
DMA transfer request enable register 3 is initialized by a power-on reset or in deep standby mode.
Bit: 7
6
5
4
3
2
1
0
ADC
MTU2
4ch
MTU2
3ch
MTU2
2ch
MTU2
1ch
MTU2
0ch
RCAN-ET RCAN-ET
1ch
0ch
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
7
ADC
0
R/W DMA Transfer Request Enable Bits
6
MTU2 4ch
0
5
MTU2 3ch
0
4
MTU2 2ch
0
3
MTU2 1ch
0
2
MTU2 0ch
0
R/W These bits enable/disable DMA transfer requests, and
R/W ^{enable/disable CPU interrupt requests.}
R/W
0: DMA transfer request disabled, CPU interrupt
request enabled
R/W _{1: DMA transfer request enabled, CPU interrupt request}
R/W
disabled
1
RCAN-ET 1ch 0
R/W
0
RCAN-ET 0ch 0
R/W
Rev. 2.00 Sep. 07, 2007 Page 136 of 1312
REJ09B0320-0200