SH7261 Datasheet, PDF (23/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

19.3 Mailbox.............................................................................................................................. 815
19.3.1 Mailbox Structure ................................................................................................. 815
19.3.2 Message Control Field .......................................................................................... 817
19.3.3 Local Acceptance Filter Mask (LAFM)................................................................ 821
19.3.4 Message Data Fields ............................................................................................. 822
19.4 RCAN-ET Control Registers ............................................................................................. 823
19.4.1 Master Control Register (MCR) ........................................................................... 823
19.4.2 General Status Register (GSR) ............................................................................. 829
19.4.3 Bit Configuration Register (BCR0, BCR1) .......................................................... 832
19.4.4 Interrupt Request Register (IRR) .......................................................................... 837
19.4.5 Interrupt Mask Register (IMR) ............................................................................. 843
19.4.6 Transmit Error Counter (TEC) and Receive Error Counter (REC)....................... 844
19.5 RCAN-ET Mailbox Registers............................................................................................ 845
19.5.1 Transmit Pending Register (TXPR0, TXPR1)...................................................... 846
19.5.2 Transmit Cancel Register 0 (TXCR0) .................................................................. 849
19.5.3 Transmit Acknowledge Register 0 (TXACK0) .................................................... 850
19.5.4 Abort Acknowledge Register 0 (ABACK0) ......................................................... 851
19.5.5 Data Frame Receive Pending Register 0 (RXPR0)............................................... 852
19.5.6 Remote Frame Receive Pending Register 0 (RFPR0) .......................................... 853
19.5.7 Mailbox Interrupt Mask Register 0 (MBIMR0).................................................... 854
19.5.8 Unread Message Status Register 0 (UMSR0)....................................................... 855
19.6 Application Note................................................................................................................ 856
19.6.1 Configuration of RCAN-ET ................................................................................. 856
19.6.2 Test Mode Settings ............................................................................................... 861
19.6.3 Message Transmission Sequence.......................................................................... 863
19.6.4 Message Receive Sequence .................................................................................. 865
19.6.5 Reconfiguration of Mailbox.................................................................................. 867
19.7 Interrupt Sources................................................................................................................ 869
19.8 CAN Bus Interface............................................................................................................. 871
19.9 Usage Notes ....................................................................................................................... 872
19.9.1 Module Standby Mode.......................................................................................... 872
19.9.2 Reset ..................................................................................................................... 872
19.9.3 CAN Sleep Mode.................................................................................................. 872
19.9.4 Register Access..................................................................................................... 872
19.9.5 Interrupts............................................................................................................... 873
Section 20 IEBus Controller (IEB) [R5S72612] [R5S72613] ......................875
20.1 Features.............................................................................................................................. 875
20.1.1 IEBus Communications Protocol.......................................................................... 876
20.1.2 Communications Protocol..................................................................................... 880
Rev. 2.00 Sep. 07, 2007 Page xxiii of xxxii