SH7261 Datasheet, PDF (643/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
Initial
Bit
Bit Name Value R/W Description
1, 0
OS[1:0]
00
R/W Output Select 1 and 0*²
These bits select a method of TMO pin output when
compare match A of TCORA and TCNT occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A occurs
(toggle output)
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.
2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first
compare match occurs after resetting.
• TCSR_1
Bit
Bit Name
7
CMFB
6
CMFA
5
OVF
Initial
Value
0
0
0
R/W
R/(W)*¹
R/(W)*¹
R/(W)*¹
Description
Compare Match Flag B
[Setting condition]
• When TCNT matches TCORB
[Clearing condition]
• When writing 0 after reading CMFB = 1
Compare Match Flag A
[Setting condition]
• When TCNT matches TCORA
[Clearing condition]
• When writing 0 after reading CMFA = 1
Timer Overflow Flag
[Setting condition]
• When TCNT overflows from H'FF to H'00
[Clearing condition]
• When writing 0 after reading OVF = 1
Rev. 2.00 Sep. 07, 2007 Page 611 of 1312
REJ09B0320-0200