SH7261 Datasheet, PDF (472/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.18 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables/disables output settings for output pins
TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly
if the TOER bits have not been set. Set TOER of channel 3 and channel 4 prior to setting TIOR of
channel 3 and channel 4.
Bit: 7
—
Initial value: 1
R/W: R
6
5
4
3
2
1
0
— OE4D OE4C OE3D OE4B OE4A OE3B
1
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7, 6 —
All 1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
5
OE4D
0
R/W Master Enable TIOC4D
This bit enables/disables the TIOC4D pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
4
OE4C
0
R/W Master Enable TIOC4C
This bit enables/disables the TIOC4C pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
3
OE3D
0
R/W Master Enable TIOC3D
This bit enables/disables the TIOC3D pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
2
OE4B
0
R/W Master Enable TIOC4B
This bit enables/disables the TIOC4B pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
1
OE4A
0
R/W Master Enable TIOC4A
This bit enables/disables the TIOC4A pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
Rev. 2.00 Sep. 07, 2007 Page 440 of 1312
REJ09B0320-0200