SH7261 Datasheet, PDF (1044/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 22 A/D Converter (ADC)
Figure 22.1 shows a block diagram of the A/D converter.
Module data bus
Peripheral
bus
AVcc
AVref
AVss
10-bit
D/A
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
+
–
Comparator
Sample-and-hold circuit
Control circuit
ADTRG,
conversion start trigger
from MTU2 or TMR
ADI
interrupt
signal
[Legend]
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
ADDRE: A/D data register E
ADDRF: A/D data register F
ADDRG: A/D data register G
ADDRH: A/D data register H
Figure 22.1 Block Diagram of A/D Converter
Rev. 2.00 Sep. 07, 2007 Page 1012 of 1312
REJ09B0320-0200